The present invention relates in general to semiconductor devices, and more particularly to a system and method for addressing junction capacitances in semiconductor devices.
Semiconductor processing has become increasingly important in today""s society. Generally, semiconductor manufacturers strive to improve processing or fabrication methods for electronic devices, which result in greater efficacy and overall speed in semiconductor products and components. One aspect of semiconductor processing relates to the n-type and p-type bulk regions of an electronic device. In some environments, the n-type and the p-type bulk regions of a semiconductor may operate generally as a capacitive interface as an associated channel region achieves conductivity. Sharp ion concentration boundaries at these regions may result in a high capacitance associated with and existing between the n-type and p-type bulk regions. Such high capacitances may generally operate to slow circuit speed or to hinder the performance of a semiconductor device.
According to one embodiment of the present invention, a method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a semiconductor substrate. The gate conductor defines a channel region disposed inwardly from the gate conductor. The method additionally comprises forming source and drain regions in the semiconductor substrate. The source and drain regions are each disposed adjacent one edge of the channel region. The semiconductor substrate and the source and drain regions have an associated bottom wall junction capacitance. The method also comprises using a transient enhanced diffusion anneal to effect ion concentration profiles associated with the source and drain regions, resulting in an increased balance in the ion concentration profiles associated with the source and drain regions and an ion concentration associated with the semiconductor substrate. The increased balance achieves a reduction in the bottom wall junction capacitance.
Embodiments of the present invention provide a number of technical advantages. According to one embodiment of the present invention, a transient enhanced diffusion anneal step in a method of forming a semiconductor device operates to achieve approximate parity between the ion concentration of the substrate and the ion concentration of the deep source and drain regions of the semiconductor device at areas adjacent to the p-n junction. Parity refers to the creation of a wider area with a balanced ion concentration in the substrate that is not dominated by holes or electrons. This balancing or smoothing of an ion concentration profile results in a reduced junction capacitance as a vast number of n-type and p-type ions operate to cancel each other. The reduced junction capacitance may in turn operate to improve the overall speed and performance of the semiconductor device. Other technical advantages are readily apparent to one skilled in the art from the following figures, the description and the claims.